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The Progress and Challenges of Applying High k Metal Gated Devices to Advanced CMOS Technologies

Solid State Circuits TechnologiesV, is the barrier height, Tor is the physicaltric constant of the insulator and a andpre-exponential factors From thisbserve that the tox or k is thetrolling the direct tunnel current density The tunneling curredensity increases dramatically as the SiO becomes thinner In generaeakagecreases 100 times forery5 nm that the sio is thinned the gatehigh as the 10 E Amp/cm- range for SiO as thin asThe highIGIDL + Ig)Where: Isubth:IGIDL: gate-induced drain leakage currentIg: gate leakageOn the other hand, Eq [1] shows that increasing the dielectric constant of an insulatordirect tunneling current

This is because the gate oxide physicalcorrelated by the equivalentoxide thickness(EOT) definedOT=(Ksio/KinsulatorTinsulatwhere Kso and Kinsulator are the dielectric constant of SiO2 and the insulator, respectiveand Insulator is the physical thickness of the insulator Based on this definition, an insulatorterial with a five times greater dielectric constant than SiOz would require a five timesgreater physical thickness than SiO to keep the same EOT as SiOz Therefore the tunnelingald be orders of magnitude leiO2 because the tunneling leakage current decays exponentially as the insulator becomesthickerreater than the metatunnels from the metal elede into the insulator conduction band first and then travelsward the other semiconductor electrode This is known as the Fowler-Nordheim(FN)tunnelfor FN tunneling current densityVa3/2 To)=D exp(32K4)where C and D are pre-exponential factors From this equation, onbserve that thebarrier height is the dominating factor in controlling the FN tunnel current densitypares the exponent (the product of m, Vh, and k) shown in the equdirect tunneling (low field) and Fn tunneling (high field)for insulatorrials withdifferent Va and K values The results show the followingtoincrease the dielectric constant, the reductioo be used for highly scaledpure nitride) shown in the table, thshown in the direct t

to Advances s amos Tacngolsgieb Lateral Oxidation Model [171ed at the edge of theXTEMormation during a high temperature anneal such as a/drain anneal Oxidationlarge devices is insufficient to prevent the formation of nodules, whichluse high leakage current

PMOS Capacitorlum from Edge0Metal oxideSi Substrate

Solid State Circuits Technologiesit is still a challenge to achieve an EOtfter transistor fabrication Degradation in device mobility is observed wlmelectric This is more problematic for low EOT applications Since compatibility withnd metal gatehas several advantages, a high-k/metal gate stack is the choice for advancekey issue for metal gate materials research is controlling the work function of metal gateectrodes after CMOS processing There are two choices of metal gate implementation TheCMoS devond type is a dual metal gate electrode with one metal having a workfunction(4, 1 ev)near the conduction band of the silicon substrate (Ec) for NMOS and theother one having work function (-5 2 ev)near the valence band of the silicon substrate(efor PMOS(Figure 16) The metal electrode materials should have thermal, chemical,cessing It is desirable to haywith CMOS Process integration, either a conventional"gate first or replacement" gate lastapproach

Metallicpounds (nitrides, silicides, carbides, borides, etc ), andsolid solutions are possible candidatesNMOSqm4I evo41 evqoB qx=41evqm=52 evEcEEError_FSiliconN+ Poly-si Insulatork functionsbe obtained from moScaps of various oxide thicknesses using thellowing equation:Vab- dMs+ QF/CoAn intersect in theof thersus EOT plot is the work function(Figure 17) Table 2

to Advances s amos TacngolsgieApplying High-k/Metal-Gated DevicesZrN/SiO2vFa"中 vss/x中ws“中n[xE2…kTnN/]中中4620 voltso ch7,433,46367425Zrsi2425,464154TaN5,44


Solid State Circuits Technologiesmethod and film proMetal depcaffect the metal filmproperties such as resistivity, microstructuredhesion Deposition processes such as CVD and PVD are common methods In general,CVD films provide better conformality and negligible damage compared to PVD films, brformality, but throughput is low

Figuresdeposition process on device perfoThe deviceer mobility than Cvd tin ohigher gate leakage current than devices fabricated with CVD and ALDEeff(MV/cm)TiNSIO,(30A)s N,-800t+H-for看

The ProgChallenges of Applying High-k/Metal-Gated Devicesto advane58PMOSon(mostlyfrom CVD)and plasma dafrom PVD) affect gate deters suchDit V, stability, and gate oxide integrity Another concern with metal gates is poor oxidationresistance The etchability of metal materials, especially selectivity to metal oxides, is a keynal"Gate First"CMOS IntegrationConventional gate first integration involves the ability to etch the gateexample, Figure 20nitride/W/Tin gate electrode stack on topThe gate electrode materials must be protected from oxidation or attacelectrode materialg high temperature steps

These reqlimitmaterials for metal gate materials alith alternative high-k dielectTiN W Resistoκ ido and/orN⊥七rideGateoxidesubstracts七ep1stcketFig2028,29placement "Gate Last"CMOS Integrationhis integration eliminates many constraints posed by conventional"gate firstconventionalT fabrication with replacement polysilicon, gate oxide is depositedd using chemical-mechanical polishing(CMP) technflatten the top surfaceigure 20a), A wet etch or dis used to etch off the polysilicon gate(Figure 20b) followed by a new metal gate electrode material and adielectricdeposition(Figure 20c) Another CMP process or a second patterning of the gate is used

Solid State Circuits Technologiesaeisi i silicon substrateFill silicon substratemet-1hin tin oxideS sIllcon substrateA single metal gateid-gap work function may not be able to achieve a lotOSFET threshold voltage and boost performance; however, it has potential for fullydepleted silicon-on-insulator(FDSOI)applications Dual metals with work functionssimilar to n* polysilicon and p*polysilicon pose significant integration challengesThermodynamic and mechanical stabilitn the choice of metalls Both the gate first and gate last integrationdisadvantages The final choice of integration scheme will be decided by perfd3 Device characteristics using High-k/Metal Gate(HKMG)stack31 Impact of defects in the HKMG stack on device performance and reliabilityAs mentioned in section 2

11d, the deposited high-k gate dielectric contains a high defectbetween silicon andtional thermally grown gateA TEM cross-section ofthe HKMG gate stack, shown in Figure 21, highlights the different regions of the gate stackThe defects in the bulk of the high-k gate dielectric and at the interface between the silicorsubstrate and IL have a significant impact on deviceand relialsuchthreshold voltage stability As discussed in Section 212aiii, the best candidate for a high-kdielectric is Hf-based metal oxide, Therefore the following discussion is based onHfO2/ metal gate stack

to Advanced amos TecnglsgitMetalGate30AHigh-K0A311 Si/IL interface improvement- stressed relaxeddesirable because we need a thin g the advantageDepositing high-k on top of thick, high quality, thermally groyistor speed To solve this problem, a stress relieved pre-oxide(SRPO)processhas been developed tore the interfacial properties between the high-k dielectric andilicon substrate while maintaining the required thinness to meet the speed enhancemenrequirement for integrated circuits The experiment discussed here is as follows The SRPOhe thermal oxide back to 10 A using a diluted 700: 1 hydrofluoric acid: H20 solutionTheHfO2 is then deposited by ALD After the high-k dielectric undergoes a PDA, a TasiN metal00C was used to fabricate metal gate/high-k stack nMOSFETs on bulk silicon [32]

Fig 22spares the threshold voltage (Vo) shift under cess(an rCA clean followed by ALD HfO with a Tasin metal gate)nd the new SRPO procesth a TasiN/HfO2 gate stack for short channel devices10 um/015 um) The SRPO with a TaSiN/HfO stack results in a 3X smaller Vi shift than thestandard process These results suggest that devices with the standard process sufferocess-induced gate edge damage during transistor fabrication, which increases the V, shiftgreater trap ginducedignificantly when using SrPo due to the high quality interfacial layer under the HfOwhich suppresses interface trap and border trap generation during constant voltage stressTo acess-induced gate edge damage, the charge pumping current was measured on33] under drainbias to detect local charge at the gate edge The results show lessterface and border state trap density for HfO/SRPO devices than for HfO/RCa devissed charge pumping resultore robust than the rctreatment under process-induced local charge genshort channel devices with SRPO is higher than the standard pre-treatment due to betterterface properties with the SRPO process The fundamental difference between a chemical

Challenges of Ap

plying High-k/Metal-Gated Devicesequation is only about two times greater than that for SiO while the exponent shown in2 On the other hand, it is clear that an insulator with a K value of 25 reduces the expoolingsignificantly in the direct tunneling Eq

[1 and more than two times in the FN tunK「 LowField「 High Field I78Ta2O%,HfO_,ZrO2-45921 SiO2/Polyschematic of a MOSFET in which the gate oxide is SiO2 andectrode is doped polysilicon Figure 2 shows the equivalent circuit of an MOSThe total MOS capacitance CKwhere Cor is the oxide capacitance, Cs is the silicon capacitance, and Cp is the polysilicon gatetrode depletiPoly-Si GateGate OxideGOX

Solid State Circuits TechnologiesWhen the mOSFET is operated in inversion mode, the doped polysilicon gate energy bandbias-dependant value of Cp andFETthe Cox for an applied gate voltage (Ve, which, in term, will degrade the MOSFoncentration in thegate oxide and induce a threshold voltage (Vi)instability problem On the other handtal gate as the gate electrode could eliminate the polysilicon gate deplpantincorporated into the gate electrode Another advantage of a metal gate is that the resistanceof the metal gate electrode is less than a polysilicon gate22 High dielectric constulatorbility with gate electrodetrodes with high dielectrnsulators raises some concern

Most metal oxides with a hish dielectric constant used aste insulator reteraction makecontrol the MOSFET threshold voltage On the other hetal gre compatible with high-k metal oxidesMaterials screening of high dielectric constant insulators and metal gatesgh-k gate dielectrissues of high-k gaSome fundamental issueementing a high-k gate dielectric in MOSFETrade-off between the dielectric constant(K) and band gap(eg)Film microstructure: crystallineaact of the amorphous interfaciai javer ali on the overall dielm, Eot scalability, interfacialness, and mosfet mobilityPossible mobility degradation and high fixed charge caused by a high-k insulatorn analysis of the Gibbs free energies governing the following chemical reactionsmetal-Si-oxygen ternary systems is important in predicting stabilityTo avoid instability with Si to form SiO,Si+M。→M+SiO2Si+M。x→Ms+siOb Trade-off between the Dielectric Constant(K) and Band Gap(Eg)From the direct tunneling Eq [1, it is desirable to find an insulator with a highgh-k metal oxides are not reported, the closest anddily available indicator for the band offset is the band gap values Figure 3shows the plot of band gap versus dielectric constant for various metal oxides

to Advanced amos TecnglsgitApplying High-k/Metal-Gated Devices6A12o38ZrSio4 HfSiO4A103La20o Bao432electric ConstantFig 3 The trade-off between dielectric constant and band gap limits the choice of metaC Film Microstructure: CrystallineAmorphouste defects/voids, which willa device yield issue In addition, oxygen, dopant, and impurities diffuse swiftly inthe polycrystalline structure primarily through the grain boundary and degrade thef the gate stack Another potentialsize among small devices and wafers

Amorphous metal oxides can reduce O anddopant diffusion and lower defectivity;dielectricconstant than those metal oxides with a polycrystallinfusion through the Grain Boundary of Metal Oxicdistinct processing difference between the metal oxides and conventionalthermal oxide sio,, Metal oxidedeposited on the silicon substrate instead ofhermally grown like SiO2 The intrinsic quality of the deposited film is inferior tothermally grown film A post-deposition anneal under dilute oxygen ambient ise devices Most metal oxides with a high dielectricne structure afteranneal Therefore the oxygned in the ambienhe post-metaldedeposition anneal diffuses through the grain boundaries of the metal oxides and reactsSiO interfacial layer (Ie Impact of the Amorphous Interfacial Layer(IL)on the Overall Dielectric Constant of theInsulator, EOT Scalability, Interfacial RoughneThe SiO2-like interfacial layer reduces the overall dielectric constant of the bi-layer gateould makescaling the EOt to less than 1 nm difficult The interface between the IL and siliconubstrate is rougher than the interface between conventional thermally grown SiOz and

Solid State Circuits Technologiesilicon, which may degrade channel carrier mobility and generate interface statedefects, Figure 4 shows a transmission electron microscopy( TEM) image of the metaloxide mos structure and the keyrns about the gate stackcompatibilityInterfacial laFig, 4f Possible Mobility degradand High Fixed Charge Caused by the High-k InsulatorSoft phonons in the metal oxide bonding structure contribute to theatomsto the overall polarizability and therefore the high dielectric constant

Therthat the mobility of the channel carriers madegraded by interactionsric Candidatesthat hadielectric constant or small band gap, theandidates fall under group IVB, IlIA, and IB of the periodic tableMetal Oxides Used for Memory Capacitors [1, 2, 3, 4Candidates such as TiO2 and TazOs have the advantage of having a relatively higdielectric constant and a history of processing in the industry However, themake them unattractive for logic devices:Small band gapnstability with siliconatesquire an oxygen anneal to improve film quality, which results in oxidationin eOt

to Advanced amos TecnglsgitApplying High-k/Metal-Gated DevicesUnstable microstructureii Group IllA and IIIB Metal Oxides: Al2O3 and La O3 5, 6ddition, Al2o3 isphous at 1000C and has a relatively high band gap(87evit has a relatilow dielectand P diffusion; and easily absorbs HzO LazO has a relatively high dielectricconstant(K 27), but the band gap is small (43 ev) and it very easilyiii Group IVB Metal Oxides: HfO and ZrO2[8-18These metal oxides have reasonably high dielectric constants and band gaps(seeFigure 3) Both ZrOz and HfOz devices have demonstrated amagnitude reduction in gate leakage with an EOT around 1

0 nm and well-behaveilicon gates than HfO2 Figure 6 shows the interfacial layer thickness beneaI temperatureases from 550 toZroIn tenciaaer550CPDA650 CPDAFig6[13Figure 7 shows the x-ray photoelectron spectroscopy (XPS)spectra of the interfaceon ZrO2 XPS reveals that ZrOz decomposes into a Zr metalgate stack is annealed in nif950C under ultra-highgh gate leakage current It alsothe formation of interfacial sio, betweD2 and the polysilicon gate during polysilicon deposition These results suggtrong interaction between ZrO2 and siHa during polysilicon deposition at 550 toOn the other hand, HfOz metal oxide is thermodynamically more stable with8 shows the XPS spectra of the interfand the polysiliconUnlike the Zro, film the HfO film remains stable afterpolysilicon deposition and a post-anneal in nitrogen up to 950C

Solid State Circuits TechnologiSi 2pPoly dep2/800CCYD Zro7518018519096100104108Fig7[141,()AgN28001216202452452853253696100b Metal Silicates(M-Si-O)19-22Adding silicon to metal oxide can maintain the amdhase up to a mediumperature such as 800C depending on the silicon concentration

These metal silicatesare thermodynamically stable with the silicon substrate Figure 9 shows the TEM crosssections of a gate stack composed of ZrSi,Oy silicate deposited on a silicon substrateth an aluminum metal electrode No interfacial laver forms between theterface is atomically sharp, and the filmannealthereible phase separwith a hid the dielectric constaner than metal oxide candidates such

to Advances s amos TacngolsgieFig9[21,22]Pulse MecPurge with N2*,I Pulse h,oMeCln+xH,oMeoIClPurge withRepecy2

13 High-k dielectric deposition techniquesAn important factor in determining the final choice of high-k dielectric is the depositionprocess, which must be compatible with current CMOSg, cost, and throughput InOCVDIand OH imprstained in the filmPhysical vapor deposition(PVD) is good fong new materials However, thearity of the target and plaolecular beam epitaxy(MBEcontrol, but the throughput isAtomic layer deposition(ALD) has high uniformity control and good conformality

Solid State Circuits TechnologiesPotential contamination with Cl, C, H, and OH impurities is alsosummary, same high-k materials fabricated by diffposition tools, processes, andresult in different properties The finalbalance cost, throughput, tool reliability, film properties, and device performance andvice integration issues [171dependence on device size At 2 V, the leakage current density for the 14 umNMOS (PMOS9x(X) that of a 1 4 um device Figure 12 shows the TEM crosssection of the PMOS capacitor with a longer gate length

It is clear thative occurred at the polysilicon/ZrO2 interface The TEM cross-section( Figure 13)showsZrO2 creates a conduction path that results in a high gate leakage current The longer gatelength results in a higher probability that conduction paths will be formed1E+06PMOSNMOS1E+031E+00g=14 umE03L E-061E09Ig=142gPMOS CapacitorZr-Silicide nodules