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Continuous Time Analog Filtering Design Strategies and Programmability in CMOS Technologies for VHF Applications

Advances in Solid State Circuits Technologiesbehaviour of the transconductor, to the extent of appearing a distortion brought abouquire to be used to minimize these effectsr balanced transconductor structures into account, distortion isnd betterbtained furtherof tuning techniques comparametelayout, a detailed study of the technology and a deep analysis of the device, lead toement in the transconductor behaviosequently, in the filter performanceThus, while developing the design of an active gm-C filter, the effects of transconductored in depth to achieve optimummplementation of the transconductor should show a trade-off between dc-gain, linearityd IAny pole or zero frequency in filters based on the Gm-C technique is of the gm/C type Thisthat there are two fundamental ways of programming the frequency respof thefilter: keeping Gm consC

or vidvantage of maintaining the noise specificationsthe entire pretion foDue to the abovensiderations, the constant-C scaling technique is the preferred approach for implementinfilters operating in a very high frequency range, focusing on the design of tunable CMOSthan continuous tuning, both to preserve the dynamic range and take advantage of theconfigures the filter a possible discrete tuning technique is based on a parallel connectionof transconductors, where the desired time-constant can be digitally programmed (Pavan etal 2000a) This approach succeeds in keeping the Q-factor constant and maintainsthe entire bandwidth settingThe target is toent a transconductor that is compatible with the lategital CMOS technologies and programmablemaintaining an adequate dynamic range(DR) The concrete values of thesedepend on each particular application This work does not focusbut on carrying out an overall analysis to seek the structure that provides thetion frequency, programmability, dynamiConsidering alloptimal solution for digitally programmable analog filters inthe VHF/UHF range is to take advantage of current-mode pseudo-differential topologies anding the transconductor parathat limit its ideal behaviour a very well-knopology(Smith et al, 1996; Zele et al, 1996)will be characterized; starting frome-Smith architecture, two different transconductors will be presented and in-depthwill be carried out, following which all the characteristic parameters of each active cellbtained; programmability will then be added to the VhF transconductors and thective cell is based on a classical structure, a broad diveblecontinuously tunable CT filters can be obtained, wheter is achieved due to the design of a generic prograof special capacitor structures in standard digital technologies, the use of the MOS structure as

uS-Time AnaApplicatinnstrategies and ProgrThe reason for this difference is that the FC unit cell considered and shown in Fig 6(b)iscode topology To obtain similar output impedancethe mnsbe implemented by usingresistance) to reduemode gainode input resistance) and stabilizemmon-mode voltages On the other hand, the use of pseudo-differetstructurescient control over thworth noting that this structure not only stabilises the common-mode voltage, but alsoof partial positive feedback This idea has alreadybeen used for high-frequency transconductors in(Nauta, 1993) and for a clasode filters(Smith et al, 1996; Zele et alThus, considering this topology imple55 db and CmrR of 60 dBbe obtained with inherent stability of common-modees Note that themode(CM) signals in balanced circuitsuse instability and distortionurrent consumption,transconductance value are strongly dependent on the CM input signals Additionalchniques can be used in the proposed topology if a greater CMRR is needed, such asmode rejection that are capable of operating with low-voltagebtained by usditional transconductor thatBaschirotto et al, 1994; Wyszynski et al, 1994) Considering this technique, CMRR valuesup to 70 db could be obtained4

High frequency responseIn this section, the bandwidth of the transconductor will be analysed Note that if single(Fig 3), the bandwidth confinite owing to the absentthe transfer function of the integrator A more complete model of the MOs transistor dnsmission zero associatederlap parasitic capacitgd, frequency dependence ofthe transconductance gm(s) and mismatch in common-mode feedback circuits A closerexplanation of MOS behextrinsic part)is required before starting the study of the complete integrator Takins Veccount a non-quasistatic model (Tsividis, 1996), the high-frequency behaviour of thehen analysing transconductor bandwidth, several general factors must be consideredThe output of the complete transconductor may be assumed to be short-circuited for acbulk-transconductance and Cgd, Cg Cas, Cbs and Cbd &\e parasitic capacitancesgmbtheAll the unit cells are designed to seek perfect matching between them Therefore, allsimilar transistors haveperties except for transconductance gm of the Nlls shown in Fig 6) In thisidering the notation and index-linking previously used in Fig 3gm(Ni)ANgm(N); gm(N2)APBm(N); gm(N3)"gm(N) Consequently, &gm"(AN-Ap)g

Advances in Solid State Circuits Technologiesthe difference between M, and M,, or, M and M; due to the difference inand bias currents of N-transistors, which gise to the negativethat enhances the dc-gain of the systemTotal integration capacitance CI comprises not only the external capacitance, but alsottancemain contribution of these parasitic capacitances Cp and consideration of it as a greapercentage of total integration capacitance acquires great significanplemented by using dMOSpacitors, depending on the technological processt, where Gs andthets The externalext connected to thetransconductor input is in parallel with Cs For purposes of simplicity, from now on, Cswill include the equivalent capacitance of theapacitance(C,=CsCext) Therefore, total integradC,+Cp including parasitic effects, the externaltance and the equivalent-modelFirstly, a model for the V-I conversion of the unit cell is derived, in both implementations toof the bandwidth of theete transconductance cell4

1 High-frequency model of the Hs unithees the parameters associated to the impedances shown in the small-signaluivalent circuit The rest of the elements: g(N), gds(N), gas(NC), gds(PC),gm(PC), Cga(n)and Cds(NC)directly represent the parameters of the respective transistorFig 8 Equivalent high-frequencyt for the hs unit cellCi (N)=C (N)+Cs (N) C(x)=C (N)+Cu(N)+C(NC)+C (NC)C=C(PC)+CH(PC) Cut =Ca(NC)+CM(NC)+Cg(PC)C(P)=C(P)+Cd(P)+CM(P)+Cat(PC)+Ca,(PC)Table 1 Small-signal parameters for the HS unit cell

uS-Time AnaApplicatin strategies and Programmabilityigh-frequency model of the Fc unit cellThe follodel for the fshown in Fig 6(b), where X(N) are the parameters associated to the MN-trathose associated to the folded transistor, x(P) those associated to the currese associated to the currentthe folded transistor, which ismplemented with a single NMOs transistor as previously illustratedsgFig 9 Equivalent high-frequency circuit for the FC unit celluivalent circuit

The rest of the elements: gm(N), gas(PF), Cad(N) and Cds(PF)directlyrepresent the parameters of the respective transistor(P)+2C,(P)+2C(P)+C (PF)+C(PF&Mr(PF)=8(PF)+8n(PF)F)+C(PF)+Co(NS)+C(NS)+Ch(NS)43 High-frequency model of the complete transconductance celltions, thential gain of the pretransconductor cell (in both(s)s-s,(s+s,)1)(s+2Denominator factorization of Eq (8)leads to obtain two parasitic poles, -d1 and-oz, but onlyge of interest Both considerations willGHhe FC approach (5>>5 and 51>>50: 51(HS)=160000 GHz,of a pseudo-differential structure, a careful study of the common-modehaviour is mandatory Thanks to the topology proposed, th

Advances in Solid state circuitsstabilized by means of partial positive feed back as previously explained Under theseAc v3(11)is moredore shows the need to neglect parasitieration as in the differential gain equation In this andifficult to accomplish However, the approximate equaasily derived andmon-mode transfer function will be analysed Therefore(acM'yCM/BcM)<

The parasitican be calculated by using a, B,yshown in Eqs (9)and(13) As the resulting relationsook for the dot terms aximate expressions to draw conbe simplified to analyse and understand the behaviour of the transconductance cell anequency limits that are associated to second order effectsh differentiate betweenthe frequency behaviour of the proposed topology and the expected ideal respons44 HS transconf the HS unit cell, a detailed analysis of the frequencyresponse of the complete HS integrator is carried out The domterms of thesepressions are subsequently obtained in this section In order to simplify the notation, thesmall-signal parameters are redefined in table 4According to stable systems, nega-01,-o2z, -E1 and -Ez have been obtained in thetransfer functions for both implementations For purposes of simplicity, when referring tothese poles, their associated frequency (01, 82, EL, 52) will be the considered magnitude

esign Strategies and ProgrammabilityHS transconducFC transconductor8(NC)+8(N8Mp(PF)+8,(PF)8 (N)(8M(NC)+8(NC)8()(gMp(PF)8(PF)AoM Aw-8(NTable 3 Summary of the high-frequency parametersC2Cg (N)+2C3(N)+C3 (NC)+C(NC)+C(PC)(N)=C(N)+ Cs(NTable 4 Impedance parameters for the HS integratorBy analysing in detail the small-signal equivalent model for the complete HS integrator, thevalue of total integration capacitance C can be calculated by Eq (14) This definition willd to a simplifica14)Firstly, the differential and common-modelin can be expressed as followsA(4-4)+-28408Agn(N)(8((AN+Ap28(C8A(N)8n(N(8M(NC)+8△(NC)」A+Aal negative resistancened by the partial positiveof the difference Sgm=(AN- Ap)gm(N)

Theexistence of this negative resistance allows the differential dc-gain to be enhanced Parasiticsummarized in table 6 The origin of second order effects can be better understood byfocusing on their dependencea=((An-Ap)8(N))(8M(NC)+8(NC))+2g, (NC)8a (N)=2g (NC)8a, (N) (17)

Advances in Solid state circuitshere considering the dominantin the transconductance g, theTherefore, the parasitic pole an can be expressed asFollowing the same process for the other pole d, we obtainy=Cr(C,(N)+Ca(NC)+C(x))=C, C(r)=C, C (NC)02(N)+8x(NC)+8(NCC(X) C&(N)+Ch(N)+Cg(NC)+Ch(NC) C&(NC)Similar results can be obtained for theau=(0AN+A2)8n(N)(8M(NC)+8(NC)=(Ax+A)8(N)g(NC(24)Bo=52=C(X)(X) Ca(NC)45 FC transconductance celnsidering the previous studll a detailed anof the complete FCout

The dominant terms of theseparameters are redefined in table 5G1=G+28mCs+3Cg(N)+3Cs(NM(PF)+2CM(In accordance with the analysis of the small-signal equivalent model for the complete FCintegrator, parameter Cl defined in table 5, directly represents the total integraticapacitance the expression of which is the same as in the hstor Therefore the totaegrator capacitance of both integrator implementations can be calculated by Eq (26)C+3C(N)+2CFor the FC integrator, the differential and common-mode

esign Strategies and ProgrammabilityA-(4-)3A82-(4-4)3Am=-(A+A)+---181 and &z, are obtained by means of ratios among a, B and y, as in the HS implementationThe final expressions are summarized in table 6 Consequently, parasitic poles on and dz caa=(AN-A)gm(N)(gsn(PF)+8(P)+28(NS)(gM(P)+2g(P≈2g(NS(8M(PF)+2g(P)(g+8(PF)+8Am(PD)C1=(8(PF)+28(P)C6=2≈28NS(31)(C(PF)+Co(N)+C)C:(2C (P)+2C(P)+CK(PF)+C(PF))=2C, Co(P)BgMP(PF)+28,(P)8M(PF)+2g(2Ce(P)+2C(P)+Ce(PF)+C(P2C(P)equency response

acM=(A+A)gn(N)(gm(P)+8(PF)+28(N)(8(PF)+28(P)=BoM=b=(8MP(PF)+284(P))C,i 7M=y=2C Cu(P)acM(AN+Ap8 (Nprevious sections in order to draystrategies and implement a competitive and robust transconductor cell, Greatoth implementations: Cr"Cs+3Cin(N)+ 2Cout( Eq 26), where C, represents the equivalent

Continuous-Time AnaApplicatin strategies and Programmability4intended passive device is probably as old as the MOs transistor concept itself Anto implementing linpacitors 15 to usemosfet devices acitors, where the gate-oxide thickness is a well-controlled variable inhapter we will show the best way to implement key analogblocks of a high-speed system in a CMOS technology with a wide programmablees andof CMOS filter design at very high frequencies and this studyd practical problemsthe drobust,time filters with very high bandwid ths implemented in low-cost2 The Integrator: building-block in the gm-C techntime(CT) integrated filtersrequired, present a frequency response controlled by time-of the simplest implns for these factors is taking advantahe integrator structure Therefore, the integrator is the dominant building blockgh-frequency active circuit design techniques, and its frequency response and lin nanynearlydirectly determine the filter perfoAccordingly, systems based on the gm-C technique are the first option for implementing CIacceptable performance over the VHF range, The active buildingelement used by the gm-C filter approach, basedansconductor cell (Fig 1),which ideally dproportional to thewhere gm is the transconductance of the element

When a grto the output node of the transconductor i

n order to take this current out, an integidealhas been obtained with a simple transcendsecond structure can be considered taking into ascurrent-modeereby two differenmpletelyd In this case, the input current is takecitance in order to obtain the transconductor input voltage and then, after the activecell, the output current Thus, Fig 2(b) shows the Iin-lo conversion

Advances in Solid State Circuits TechnologiesDue to the grounded location of most parasitic capacitors of the active cell (the totalpacitance, dependingconstituting a percentage of theintegratiewhenidering the proposed transconductor as an integrator where total integrationpacitance Cl is constituted only by these parasitic capacitances, with no need for anyexternalacitancesepending on theirontribution, the total linearity of the system will be affected As technologicavariations will also affect the value of these parasitic capacitances, sensitivity to thesecitorstailed study of the device models and integration technologyThe ideal integrator has an infinite dc-gain and neic effects, thus obtaining a phase ofr/2 for all the frequeThe uOr"gm/Cl Nevertheless, a realnductance gout and parasitic polesnd zeros, which distort the transfer functionH(s)where Apc"gm/gout is the dc-gain and Gn"@/Arc gout/C is the frequency of the dominantpole The effects of parasitic poles and zeros at frequencies much higher than the frequencyrange of the transconductor can be modelled with a single effective zero 2: positive @2results in an effective parasitic RHP-zero and negative @2 in an LHEtransconductor output conductance gout causes finite dc-gain in real integrators inthe filter In addition, parasitic poles and zeros in the integrator transfer function, togetherwith finite Apc, generate deviations of the inverter integrator phase response from -t/2, andfilters

In particularase deviations around oin the filter transfer, dependingfilter quality factors The atf the overall frequthe filter dependw closely the individual integrators in the filter follow the ideal response The filteremains very close to the ideal one if the integrator phase at its unity-gain frequency (ual to its ideal value -/2; the amount by which the phase at o deviates from thisquantity will be called A(Gx)p(a,)△o(an)=tan1|ading phasethe integrator create lagging(o>0, RHP-zero) or leading(@2<0, LHP-zero) phase errors Thease value of Aop(o)depends on the specifications for the high-frequencyconductorThe intr can be modelled with a frequency-dependent integratoractor Qint(Nauta, 1993), concluding that a high andte filter quality factorputs strong constraints on the integrators phase error, i e on Q

esign Strategies and ProgrammabilityThe filter perforis dominated byperformance of the transince thefilter specifications (dynamic range,ation and chip area) dependproperties (Q, cut-off frequencynce level) but also on transcon(ADcωuseful to put effort into the study of a high-performance transconductor thats specifications, in order to obtain a proper design for these VHF filter building3 Fully-balanced pseudo-differential transconductor celIn this section, the development of a fully-balancedharacterized by loupply noise and VHf potential application Fig 3 shows the conceptual scheme of the Zele-balanced transconductance cell arranged for using a current-mode integratorFig 3 Conceptual scheme of the complete fully-balanced current-mode transconductorTo understand the basic operation we analyse the simple first-order model of the proposeddering each unit cell as a simple transistor, ie, single comstages as shown in Fig

4 Under these conditions, the small-signal analysis gives thepression for the differential gain of the integrathe i-celltransconductance and go is the sum of output conductances gasi at the input nodee transconductor staiBy analysing this expression and considering a first-order approximation, i e, neglecting thegds effects of each transistor, an infinite dc-gain is achieved if perfect matching is obtainedbetween gml and gm2, so that &gm"gml-gm20 Nevertheless, the effect of the output

Advances in Solid State Circuits Technologiesconductances is not avoidable and the implementation of a negative resistance (ogm<0topology, provides the possibilitythat by making &gm+go-0, then Apd-o0, In practice, mismatching between transistorslimits the differential gain by up to 55 dB at most Another equivalent way for analysing thismprovement is to consider the differential-mode input resistance of the transconductor cellAs a result, this scheme shows the basic pseudo-differential structure obtainednsidering two dual transconductor cells (gm), leading to current integration through inputpacitance Cl Thanks to the additional negative resistance shown in grey in the safigure, dc-gain is increased by providing positive feed back compensation for the signalrrent and boosting the input resistance of the transconductorbe less than unity to guarantee stabilityin closed-loop configurations, is constrained by device ratios to a stable value over alfrequencies (Eq 6) Common-mode stability is assured by designing (gm1+gm2)/gm>1Common-mode behaviour analysis can be also carried out by calculating common-modeInput resistance2(8provides both a naturally high differential gain and low common-mode gain for thetegrator, improving these limits attached to a real integrator structure

Consequently, thebasic operation of the transconductor will be best understood by explaining, first, that then-mode control and dc-enhancement circuitry is connected at thend then that the linear v-i conversion mechanism occurs in theThe gain of the basic current integrator is independent of the supplythe firstorder approximation When fully-differential current topologies are used, the smallremaining supply noise feedthrough is common to both sides of the signal and thus has nodirect effect, except through random device mismatch Therefore, the integrator has goDevice mismatch can be minimized with careful layout andign techniques to around 0 1-1ly applications(Croon et al, 2002; Otinansistors(no internal nodes), results in a proper frequency response because the onlyt the inputs and at the outputs To a first-order aor zeros exist in the differential ac-response of the basic integrator circuit Both differentialode gains can be independently set by the different values of gmt and gm2The ideal integrator function is a result of setting &gm+go=0 and the phase error at the unitycalculatedΔ≈tan8

fn tos secimelogies for vAFApplicatin strategies and Programmability4To summarize, infinite differential input impedance can be obtained if 8gm+go-0 whileximizing the differential dc-gigmi+gm2) Consequently, the common-modeCMRR)portant concept should be borne in mind: as the dc-gain depends on the)e the structured to instability if this quantity becomes negative(total negative input conductance)due tompensationthe small signal model oftransconductor topology (Fig 4), the need to solfeedforward ac-current path from the gate(input)to the drain(output), through the overlaphen considering the stages forming the negative resistance, the

, 2001), the inductor shuntaking technique(Mohan et al, 2000), the capacitition techniqumplification technique(Ahn et al 2002)and the active inductor technique(Sackinger et000) They all have the advantages of low-voltage compatibility and low area; however, theutions considered in this work will be the use of cascode structures together with thDifferential systems allow the Ce-cancellation technique, ueedbackpositiyThese Ce caof dummattransistors used in a cross-coupledto neutralize the feed back action of these milleropposite sign inpthus expanding the bandwidth of the transconductor At theacitor C will cancel the Miller effect and a lotfective capacitance is obtained due to the reduction of the feedforward effect Thishat is precisely the same as the one flowingthrough the Miller capacitance Cgd and, in consequence, the neutralization capacitor musttch precisely howis remarkable that ctage-dependent and compensationly work with small signals In the case of mismatch between Cgd and Ce parasitic zeroause a small phaseHowever, this is not the full story of the high frequency behaviour of the transconductor cellIn addition, high frequency models of theMOS transistor show that gm is not independent of frequency, but has a finite delay gm(s)

Advances in Solid State Circuits TechnologiesFig 5 Cancellation of trargm/Csd and neutralization of the Miller effect: CeIncellation techniqueoff at very high frequencies Although the frequency where this roll-offthe ghzthe phase shift from this effect can become significmuch lower frequencies Since most active filters are very sensitive to small phase changesrtant to take this effect intThe first way to minimize these effects is to eliminate the internal nedesign them-impedance nodes This procedure can be carried out byimpedance node, ie

, to the low-gain point of the cascode transistTherefore, an enhancement of the integrator dc-gain has beenith this topologyof the transconductor and keeping the common-mode gain lower than unity With regard tocy limit-related problems, transmission zero has been reduced by using Ce-capacitorwhich will also reduce thency draw backs associated to the internal nodes of otherpologies by avoiding internal high-impedance nodes in the signAs a result, a low-voltage transconductor with high linearity, very high operation frequencyefficiency has beenof using cascode stages instead of singleality factorof the integrator is expected due to the higher differential dc-gain(Abidi, 1988) Basicascode circuits require high supply voltages to operate due to the largeshold voltages However, variations of the cascoique exist which can be usedwing cascode(Hs)nd the folded cascode(FC)stage(Baker et al, 1998; Sansen et1999: Sedra et al, 2004) Tcells replacing theare shown in Fig 6 The complete fully-balanced current-mode transconductance ceplemented by using thode stages are de

esign Strategies and Programmabilitya)b)Fig 6 Unit transconductance cell: (a) high-swing(HS)and(b)folded cascode(FC) topologyFig 7(a) shows the transconductor arranged for using the current-mode integrator describedusing high-swing cascode stag(Baker et al, 1998; Sanet al, 2004)

As illustrated in the correspondingHS unit cell(Fig 6(a))mplemented by using high-swing cascodeements The substrate terminals of nmos transistorsconnected to the referenceoltage as usual, and those of the PMOS transistors are connected to thenode of each transistorThe use of high-swing cascode elements offers as high accuracy as using basic cascodetages to implement each unit cell of the transconductor but, because of the slightly differentconnection between transistors, needs lower supply voltage and has fewer internal parasiticresponse of the integrator The main disadvantage of the improved cascode topology is thatdue to biasing constraints, the gate-source voltages must be kept small, resulting in largerdevices for a bias current leve32 Folded cascode sectcascode sections( Sansen et al 1999; Sedra et al, 2004) The schematic used to describe theplete integrator basedNMOSistors are connected to the reference voltage as usual, and those of PMOStransistors, both those used to implement current sources IBIAs and those implementinglded transistors mpFlThe use of folded cascode elements exhibits a substantial improvementbecause of the increased drain-voltage of the transistors, at the cost ofurces and bias voltages, Another significant benefit of using theseavoiding the biasing constraints associated to the high-swing cascode structure, we obviatethe need to keep gate-source voltages low, which results in smaller and simpler devices fogiven bias current level, lower voltage supply and larger unity-gain frequencies

Advances in Solid State Circuits Technologiesloas上Fig 7 Fully-balanced pseudo-differential current-mode cell, based on(a) high-swingonductor33 Genn order to simplify the despology analysis Assuming ideal behaviour for the integrator, the balanced input currene Cl Diode-connected sadequately biasnal current flowing into Mia and boost the inpRegarding the gain enhancement byTheoretically, the dc-p

(Nauta, 1993), in order to obtain reasonably high dc-gain valuesode transcendgain could be infinity by adjusting the equivalent negative resistance,but in practice mismatching limits the dc-gain by about 40 dB in single transistidentical bias conditions by mearmismatching sensitive design Neverthelbetween the hs and the fc cascode structureh output resistance is directlyteed thanks to the true cascode outputtage exhibited by the Hs transconductor Therefore, positive feedback compensation isot necessary to boost differential resistance or enhance the dc-gainOn the other hand, the output-node for the FC transconduenode, and the negativenecessary to obtain real inptenhancement In this approach, positive feedback compensation for the signalwing into M3,6 is essential, boosting theresistance of the integrator and